Memory control system

Details Memory control system Memory control system

2005-03-29

2005-03-29

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S324000, C713S601000

Reexamination Certificate

active

06874095

ABSTRACT:
The processor, upon fetching a sleep command, stops its own operation and outputs an internal power-down signal. The power-down control circuit outputs, upon receiving the internal power-down signal from the processor, a control signal to put a volatile semiconductor memory connected to the system bus into a self refresh mode. Thus, the processor can simply fetch the sleep command to put the semiconductor memory into the self refresh mode. Since system programs need not include any processing program for putting the semiconductor memory into the self refresh mode, the software processing can be prevented from being complicated. As a result, it is possible to reduce the burden on the program developers.

REFERENCES:
patent: 5335201 (1994-08-01), Walther et al.
patent: 5623677 (1997-04-01), Townsley et al.
patent: 6088762 (2000-07-01), Creta
patent: 6321313 (2001-11-01), Ishii et al.
patent: 6629224 (2003-09-01), Suzuki et al.
Patent Abstracts of Japan of JP 10-133960 dated May 22, 1998.

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