Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2008-10-01
2009-06-16
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000, C365S230080, C365S233100, C365S233500, C327S002000
Reexamination Certificate
active
07548470
ABSTRACT:
A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided.
REFERENCES:
patent: 7245553 (2007-07-01), Lin et al.
patent: 2003/0086303 (2003-05-01), Jeong
patent: 2004/0151053 (2004-08-01), Peterson
patent: 2006/0140022 (2006-06-01), Lee
patent: 2007/0257717 (2007-11-01), Yoon
Hsu Winston
Nanya Technology Corp.
Pham Ly D
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