Memory control method and memory control apparatus for...

Details Memory control method and memory control apparatus for... Memory control method and memory control apparatus for...

2007-05-22

2007-05-22

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S204000, C711S213000

Reexamination Certificate

active

10862345

ABSTRACT:
A signal generator detects a stage in which a central processing unit (CPU) reads an interrupt vector number from an instruction controller based on an address on an address bus and generates an address of a ROM to which the CPU makes access subsequently. The generated address is defined as a pre-reading address and this pre-reading address is supplied to the ROM via a selector before the CPU starts accessing to the ROM. In this case, an output buffer is turned off. Thereafter, when the CPU starts accessing to the ROM, the selector is switched and the output buffer is simultaneously turned on so that the address on the address bus is supplied to the ROM.

REFERENCES:
patent: 5835754 (1998-11-01), Nakanishi
patent: 6249858 (2001-06-01), Hayakawa et al.
patent: 6523110 (2003-02-01), Bright et al.
David A. Patterson and John L. Hennessey; “Computer Organization & Design”; 2ndEdition; 1999; pp. 430-433.

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