Memory control device having less power consumption for backup

Electrical computers and digital processing systems: support – Computer power control

Reexamination Certificate

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Details

C365S229000, C365S228000

Reexamination Certificate

active

06981159

ABSTRACT:
When power stoppage of a main power supply is detected during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.

REFERENCES:
patent: 5640357 (1997-06-01), Kakimi
patent: 6065124 (2000-05-01), Lee
patent: 6212599 (2001-04-01), Baweja et al.
patent: 6317657 (2001-11-01), George
patent: 6848058 (2005-01-01), Sinclair et al.
patent: 6874095 (2005-03-01), Usui

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