Memory control device for controlling transmission of data...

Details Memory control device for controlling transmission of data... Memory control device for controlling transmission of data...

2007-03-13

2007-03-13

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000, C365S189050

Reexamination Certificate

active

10395386

ABSTRACT:
An ASIC that includes a data latch for latching a data signal from a CPU and a buffer for holding the data signal output from the latch. When presently latched signal is at a higher electric potential than the data signal outputted to the buffer, that is, when then the data signal from the CPU changes from an H state to an L state, then the ASIC delays output of the buffered data signal to a memory (a pair of DIMMs) for one or more periods of the synchronization clock.

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