Memory control device

Details Memory control device Memory control device

2011-03-08

2011-03-08

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S154000, C711S156000, C711S202000, C711S221000

Reexamination Certificate

active

07904677

ABSTRACT:
A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

REFERENCES:
patent: 5978875 (1999-11-01), Asano et al.
patent: 6067632 (2000-05-01), Yamaguchi
patent: 6671289 (2003-12-01), Tamura et al.
patent: 7295553 (2007-11-01), Saitoh
patent: 7606249 (2009-10-01), Swenson

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