Memory control device

Details Memory control device Memory control device

2011-02-08

2011-02-08

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C711S105000, C711S106000

Reexamination Certificate

active

07885133

ABSTRACT:
A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).

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