Memory control device

Static information storage and retrieval – Read/write circuit

Patent

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Details

36518904, 36518905, 365194, 36518908, G11C 700

Patent

active

052335577

ABSTRACT:
A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.

REFERENCES:
patent: 4815039 (1989-03-01), Tai et al.
patent: 5022011 (1991-06-01), Allan
patent: 5031150 (1991-07-01), Ohsawa

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