Memory control device

Details Memory control device Memory control device

1994-08-11

1995-12-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

36518912, 365219, 365239, 365240, G11C 700, G11C 800

Patent

active

054774900

ABSTRACT:
An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.

REFERENCES:
patent: 4435792 (1984-03-01), Bechtolsheim
patent: 4506348 (1985-03-01), Miller et al.
patent: 4866675 (1989-09-01), Kawashima
patent: 4876670 (1989-10-01), Nakabayashi et al.
patent: 4905192 (1990-02-01), Nogami et al.
patent: 5084839 (1992-01-01), Young

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