Memory control circuit that selectively performs address transla

Details Memory control circuit that selectively performs address transla Memory control circuit that selectively performs address transla

1995-07-28

1998-06-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Generating prefetch, look-ahead, jump, or predictive address

711 5, 711157, 711168, 711218, G11C 800, G06F 1300

Patent

active

057652120

ABSTRACT:
A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for providing address 4N+1 to blocks 0 and 1 only when the required read address is 4N+2 or 4N+3, a set of latch circuits for latching data read from each of the blocks, and a selector circuit for selecting necessary data from among the latched data and outputting it to a data bus. Accordingly, three or more blocks of memory are made readable in every latched operation.

REFERENCES:
patent: 4086629 (1978-04-01), Desyllas et al.
patent: 4319324 (1982-03-01), Johnson et al.
patent: 4378591 (1983-03-01), Lemay
patent: 4424561 (1984-01-01), Stanley et al.
patent: 5550996 (1996-08-01), Shiba et al.
patent: 5594888 (1997-01-01), Yamada

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