Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-05-12
2010-12-07
Baderman, Scott T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07849382
ABSTRACT:
An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.
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Inagaki Yoshihisa
Inoue Manabu
Izumi Tomoaki
Kasahara Tetsushi
Matsuno Kiminori
Ahmed Enam
Baderman Scott T
Greenblum & Bernstein P.L.C.
Panasonic Corporation
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