Memory control circuit, nonvolatile storage apparatus, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07849382

ABSTRACT:
An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.

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patent: 6185134 (2001-02-01), Tanaka
patent: 6549459 (2003-04-01), Higuchi
patent: 6608784 (2003-08-01), Kanamori et al.
patent: 6-131886 (1994-05-01), None
patent: 2000-173289 (2000-06-01), None
patent: 2002-108720 (2002-04-01), None
patent: 2002108720 (2002-04-01), None
patent: 2002-133892 (2002-05-01), None
patent: 2003-076615 (2003-03-01), None
U.S. Appl. No. 10/597,650 to Kasahara et al., filed Aug. 2, 2006.
U.S. Appl. No. 10/598,307 to Nakanishi et al., filed Aug. 24, 2006.
U.S. Appl. No. 11/568,470 to Tamura et al., filed Oct. 30, 2006.
English language Abstract of JP 2003-076615.
English language Abstract of JP 2000-173289.
English language Abstract of JP 2002-133892.
English language Abstract of JP 6-131886.
English language Abstract of JP 2002-108720.

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