Memory control circuit, memory device, and microcomputer

Details Memory control circuit, memory device, and microcomputer Memory control circuit, memory device, and microcomputer

2007-02-06

2007-02-06

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C714S005110

Reexamination Certificate

active

10715366

ABSTRACT:
First and second latch circuits store “0” and “1”, respectively, by reset. An output signal from the first latch circuit is input to the second latch circuit. Register setting data is input to the first latch circuit via a first gate that allows an input signal to pass through when the output signal from the second latch circuit is “1”, and outputs “0” when the output signal from the second latch circuit is “0”. A write signal is supplied to a memory via a second gate that allows the input signal to pass through only when the output signal from the first latch circuit is “1”. When the register setting data indicates “0”, the output signals from both the first and the second latch circuits become “0”, and until being reset, the write error protect state is maintained.

REFERENCES:
patent: 4580246 (1986-04-01), Sibigtroth
patent: 5973968 (1999-10-01), Schu et al.
patent: 5991197 (1999-11-01), Ogura et al.
patent: 6285583 (2001-09-01), Cleveland et al.
patent: 6366512 (2002-04-01), Yeh et al.
patent: 2005/0038924 (2005-02-01), Takahashi
patent: 11-120781 (1999-04-01), None

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