Memory control circuit and memory control method

Details Memory control circuit and memory control method Memory control circuit and memory control method

2006-12-21

2008-10-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S238500

Reexamination Certificate

active

07440338

ABSTRACT:
A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.

REFERENCES:
patent: 6721212 (2004-04-01), Sasaki
patent: 7184322 (2007-02-01), Takahashi et al.
patent: 2007/0153576 (2007-07-01), Oh et al.
patent: 06-266614 (1994-09-01), None

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