Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2003-01-02
2004-04-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189050, C365S189020, C365S228000, C365S226000, C326S070000, C326S071000, C326S068000
Reexamination Certificate
active
06721212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory control circuit for controlling a plurality of memories corresponding to a plurality of logic interfaces, respectively.
2. Description of the Background Art
A controller incorporating a CPU (central processing unit) usually requires two kinds of memories: nonvolatile memories such as a ROM (Read Only Memory) for storing an activation program, initial data and the like and a flash memory (hereinafter, referred to as “boot memory”), and volatile RAMs (Random Access Memory) used for storage of loaded programs and temporary storage of variables. The controller and these memories are interconnected via a bus, and as a logic interface standard for connecting these controller and memories, TTL (Transistor—Transistor Logic) and LVTTL (Low-Voltage TTL), SSTL (Stub Series Terminated Logic), LS-TTL (Low power Schottky-TTL) and the like are employed.
Each memory has an input/output interface (level shifter) for converting an input voltage into an internal voltage and converting the internal voltage into an output voltage according to the logic interface. For example, according to the LVTTL standard defined by the standardization organism JEDEC (Joint Electron Device Engineering Council), with respect to a source voltage V
DD
, input voltages that are determined as “high level” (V
IH
) are defined in the range of 2 V (volts) to V
DD
+0.3 V (volts), input voltages that are determined as “low level” (V
IL
) are defined in the range of −0.3 V (volts) to +0.8 V (volts), and values in the vicinity of 3.3 V are recommended as the value of the source voltage V
DD
. Also according to the LVTLL standard, the minimum value of high level output voltages (V
OH
) is defined as 2.4 V, and the maximum value of low level output voltages (V
OH
) is defined as 0.4 V.
In the case where the above-mentioned boot memory and the RAM use the same logic interface, a bus can be shared for transmitting address signals, control signals and data signals without any problems. However, if such a bus is shared in the condition that these memories use different logic interfaces and thus the source voltages V
DD
are different, a voltage higher than the input withstand pressure is applied to a memory supporting lower source voltage, causing a latch-up and the like, which triggers a breakdown in the input/output interface, instability of operation of the memory and the like problems. In order to avoid such problems, the bus wiring can be arranged individually and separately for each of the memories using different source voltages V
DD
.
FIG. 13
is a schematic view showing one example of a memory control circuit adopting separate bus wiring for individual memories. This memory control circuit includes a controller
100
1
incorporating a CPU
101
, a boot memory
115
implemented by a nonvolatile memory, and a RAM
114
. The source voltage V
DD
of the RAM
114
is 2.5 V, the source voltage V
DD
of the boot memory
115
is 3.3 V, and these memories adopt different source voltages.
Between the controller
100
1
and the RAM
114
a first control bus
110
for transmitting address signals and control signals to the RAM
114
and a first data bus
111
for transmitting data signals are disposed, and between the controller
100
1
and the boot memory
115
a second control bus
112
which is separate from the control bus
110
and a second data bus
113
which is separate from the data bus
111
are disposed.
The controller
100
1
is equipped with a MIU (memory interface)
102
for performing memory management with respect to the RAM
114
and the nonvolatile memory
115
. The CPU
101
first issues an access request with respect to the MIU
102
when accessing to the RAM
114
or the nonvolatile memory
115
. After approving the access request, the MIU
102
fetches an address signal AD
0
and a control signal CT
0
transmitted from the CPU
101
and outputs these signals as an address signal AD
in
and a control signal CT
in
in predetermined timing.
Also the controller
100
, is equipped with a PAD circuit
105
supporting a logic interface of the RAM
114
and a PAD circuit
106
supporting a logic interface of the nonvolatile memory
115
.
The PAD circuit
105
supporting the low voltage standard of the RAM
114
has two level converters
105
A and
105
B for converting voltage level of input signal. In accessing and writing to the RAM
114
, the level converter
105
A converts the voltage levels of an address signal AD
in
and a control signal CT
in
inputted from the memory controller
103
and outputs signals after conversion to the control bus
110
via an output port
107
A for supplying to the RAM
114
. Also write data DO output from the CPU
101
is converted into data RD at the level converter
105
B and transferred via the data bus
111
from an input/output port
107
B to the RAM
114
to be written therein. On the other hand, in accessing the RAM
114
for reading, a data signal read from the RAM
114
is transferred via the data bus
111
to be inputted to the input/output port
107
B, and converted at the level converter
105
B into data RD
in
and inputted to the “1” side terminal of the selector
104
. At this time, the memory controller
103
supplies the selector
104
with a selection signal of high level. In response to this selection signal, the selector
104
selects the data RD
in
and outputs it as readout data DI to the CPU
101
.
On the other hand, the PAD circuit
106
which supports the high voltage standard of the nonvolatile memory
115
has two level converters
106
A and
106
B. When accessing the nonvolatile memory
115
for reading, the level converter
106
A converts the voltage levels of an address signal AD
in
and a control signal CT
in
inputted from the memory controller
103
and outputs signals after conversion to the control bus
112
via an output port
107
C for supplying to the nonvolatile memory
115
. Then a data signal read out from the nonvolatile memory
115
is transferred to an input port
107
D via the data bus
113
and converted to data NVD
in
at the level converter
106
B to be inputted to the “0” side terminal of the selector
104
. At this time, since the memory controller
103
supplies the selector
104
with a selection signal of low level, the selector
104
selects data NVD
in
in response to that selection signal, and outputs it to the CPU
101
as readout data DI.
In the above-described memory control circuit shown in
FIG. 13
, it is necessary to provide separate bus wirings for each memory. Therefore, the number of signal lines for buses
110
,
111
,
112
and
113
increases, which leads the problem well known in the art that the number of terminals (pin number) to be provided at the input/output ports
107
A to
107
D on the end of the controller
100
1
significantly increases. For solving such kinds of problems, a memory control circuit having a configuration as shown in
FIG. 14
can be employed.
In the memory control circuit shown in
FIG. 14
, a control bus
120
and a data bus
121
are shared by the RAM
114
(source voltage 2.5 V standard) and the nonvolatile memory
115
(source voltage 3.3 V standard). In order to prevent voltages higher than the allowable value from traveling the data bus
121
and applied to the RAM
114
, a data signal outputted from the nonvolatile memory
115
is converted into a signal conforming to the low voltage standard for the RAM
114
at a level converter
123
and then outputted to the data bus
121
.
The controller
100
2
described above includes a PAD circuit
105
conforming to the low voltage standard of the RAM
114
, a CPU
101
and a memory interface
102
. When accessing the memories
114
and
115
, as is the same with the operation of the controller
100
1
shown in
FIG. 13
, the CPU
101
first issues an access request with respect to the MIU
102
. After approving the access request, the MIU
102
fetches an address signal AD
0
and a control signal CT
0
transferred from the CPU
101
Mega Chips Corporation
Tran Andrew Q.
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