Memory control architecture for high-speed transfer operations

Details Memory control architecture for high-speed transfer operations Memory control architecture for high-speed transfer operations

1996-06-12

1998-04-07

Treat, William M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

395523, 395436, 395432, 395525, 711109, 711105, G06F 1202

Patent

active

057377618

ABSTRACT:
A subsystem architecture for direct memory access of random access memory (RAM) which performs block transfers of adjacent units of memory from one memory location to another. The architecture comprises a RAM array with write enable capability, serial access memory (SAM) registers, an alignment unit, and controller. An embodiment is described which performs bit-block transfers (BitBLTs) of pixel data within a graphical user interface (GUI) subsystem which utilizes Triple-ported Dynamic RAM (TPDRAM). The BitBLT is broken up into four cycles which handle the transfer of all possible combinations of units of adjacent memory utilizing the entire bandwidth of the port writing to RAM. The architecture allows operations to be pipelined.

REFERENCES:
patent: 5475631 (1995-12-01), Parkinson et al.
patent: 5555429 (1996-09-01), Parkinson et al.
patent: 5581733 (1996-12-01), Toda

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