Memory control apparatus having data retention capabilities

Details Memory control apparatus having data retention capabilities Memory control apparatus having data retention capabilities

1999-06-11

2000-06-13

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

36523009, 36523006, 36518901, G11C 700

Patent

active

060757310

ABSTRACT:
A first sense amplifier reads from a first memory cell array at a normal equilibrium point between a read-"0" operation and a read-"1" operation. A second sense amplifier detects data dissipation by reading data at an equilibrium point higher than the normal equilibrium point, from a second memory cell array provided for detection of data dissipation and having the same characteristic as the first memory cell array. An interrupt control circuit issues an interrupt request to a CPU so as to stop its operation. Subsequently, in response to an instruction from a memory overwrite control circuit, a write/read/erasure control circuit overwrites data stored in the first memory cell array.

REFERENCES:
patent: 5276856 (1994-01-01), Norsworthy et al.
patent: 5764591 (1998-06-01), Matsui et al.
patent: 5901103 (1999-05-01), Harris, II et al.

Affiliated with

Also associated with

Rating

Memory control apparatus having data retention capabilities does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory control apparatus having data retention capabilities, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory control apparatus having data retention capabilities will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2074712