Memory control apparatus and method using retention tags

Details Memory control apparatus and method using retention tags Memory control apparatus and method using retention tags

2005-12-12

2011-10-04

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

08032717

ABSTRACT:
A data storage control apparatus and method for reduction of traffic of an interconnect occurring in the timing of a cache miss within a CPU. The apparatus and method are realized by utilizing, as a response to the read request from the CPU, data tags DTAGs used for management of data registered to the cache memory within the CPU under the control of a local node and a retention tag used for holding secondary data indicating that the object data is not held in the cache memory of any CPU of a local node.

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European Search Report issued Apr. 2, 2009 in corresponding European Patent Application 05256412.7.

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