Memory control apparatus and method for controlling usage amount

Details Memory control apparatus and method for controlling usage amount Memory control apparatus and method for controlling usage amount

1996-02-16

1999-11-16

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711114, 711113, 711157, G06F 1300, G06F 1338

Patent

active

059875690

ABSTRACT:
A memory control apparatus interposed between a central processing unit and a memory device to store data includes a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store data which is transferred between the central processing unit and the memory device; and a cache memory control unit having a selector for selecting a cache memory to store data which is transferred from the memory device. The memory control apparatus selects a cache memory to which data is to be stored so as to almost equalize usage of the plurality of cache memories, thereby controlling allocation of the cache memories and enabling a cache memory space to be effectively used.

REFERENCES:
patent: 4458310 (1984-07-01), Chang
patent: 5418929 (1995-05-01), Tsuboi et al.
patent: 5568628 (1996-10-01), Satoh et al.
patent: 5640530 (1997-06-01), Beardsley et al.
IBM Systems Journal, "Evolution of the DASD Storage Control", C.P. Grossman, vol., 28, No. 2, 1989.

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