Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-07-02
1999-11-09
Coleman, Eric
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711104, G06F 1578
Patent
active
059830239
ABSTRACT:
A processor containing a cache memory having its storage capacity enlarged while suppressing area increases is provided. The processor includes an SRAM (Static Random Access Memory) cache memory and a DRAM (Dynamic RAM) cache memory of a large storage capacity. The SRAM cache memory and the DRAM cache memory are coupled to the processor through a processor bus. The SRAM cache memory and the DRAM cache memory transfer data through an internal transfer bus provided separately from the processor bus and having a larger width.
REFERENCES:
patent: 5561783 (1996-10-01), Vanka
patent: 5603009 (1997-02-01), Konishi
patent: 5673422 (1997-09-01), Kawai
patent: 5767865 (1998-06-01), Inoue
patent: 5835442 (1998-11-01), Joseph
Moriwaki Shohei
Toyomoto Hideharu
Yoshida Shunichi
Coleman Eric
Mitsubishi Denki & Kabushiki Kaisha
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