Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory partitioning
Reexamination Certificate
2001-02-02
2004-06-15
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory partitioning
C345S543000, C345S555000, C713S300000, C711S111000
Reexamination Certificate
active
06750871
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-27911, filed on Feb. 4, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates generally to a memory-consolidated image processing LSI (Large Scale Integrated circuit). More specifically, the invention relates to a memory-consolidated image processing LSI capable of being driven at low power consumption. Memory elements consolidated with an image processing part to constitute a memory part include ferroelectric random access memories (FeRAMs), magneto-resistance random access memories (MRAMs) and so forth.
Conventional memory consolidated image processing LSIs are designed to improve the processing speed for writing or the like, and have been scarcely taken measures to cope with the decrease of the driving power of the LSIs.
In order to access the memory part of the memory consolidated image processing LSI, a first power A is first consumed to access the page regions of the storage region of a memory, which comprises a plurality of page regions including a plurality of word regions, and then, a second power B is consumed to access the word regions. For example, referring to
FIGS. 1A and 1B
, the principle of storage in a conventional memory consolidated image processing LSI for storing image information will be described below. In
FIGS. 1A and 1B
, as an example of a consolidated memory, a DRAM will be described.
FIG. 1A
shows a display screen S of a display unit, such as a CRT (Cathode Ray Tube) or a liquid crystal display, for displaying, e.g., dynamic image data. The display screen S is virtually segmented into a plurality of page regions P. Each of the page regions P comprises a plurality of words L, each of which is, e.g., data for one line scanned in a horizontal scanning period (1H). The data thus virtually segmented on the display screen are stored in a storage region M of the DRAM shown in FIG.
1
B. The storage region M comprises a plurality of storage regions P, which correspond to the display screen S, for storing data for one line, and a plurality of word storage regions L, each of which corresponds to data for 1 H to be included in a corresponding one of the storage regions P.
Thus, the conventional memory consolidated image processing LSI is designed to store image data for one frame on the display screen S and data stored in the DRAM so that the image data correspond to the data stored in the DRAM. For that reason, in order to access the DRAM, after the storage region P for each page shown in
FIG. 1B
is accessed, each word L corresponding to a scanning line is accessed to write or read data.
Therefore, when data for a few pages must be read in order to carry out a process, such as a motion compensation, with respect to dynamic image data, the power A for accessing the pages must be multiplied by the number of the pages (P×n times×power A), and the power B for accessing the words must be multiplied by the number of required words (L×m times×power B). Therefore, the whole power consumption increases in proportion to the numbers of accessed pages and words. As a result, if the region of an image, which is required to be processed, extends over a large number of pages, the power consumption for the pages is required.
Also in image processing LSIs utilizing external memories other than the above described conventional memory consolidated image processing LSIs, a technique called tiling is used for reducing the number of accesses to a DRAM to shorten the access time. The tiling is designed to change the reading sequence of data on a display screen S although it does not change the image range. For example, the tiling takes account of the fact that the reading time is shorten by simultaneously reading two word data on the same page, wherein word data stored in another page exists therebetween, when the two word data are intended to be read. However, since the access speed is improved as the sizes of a page and a word region increase, a larger page size and a larger word size are used. However, when an external memory is utilized, the degree of freedom capable of selecting the sizes of a page and a word is small.
As described above, according to the conventional memory consolidated image processing LSIs, when a memory is accessed to cut out desired image data, excessive page regions are first accessed, and then, a desired word of the words stored therein is accessed, so that there is a problem in that vast amounts of power must be consumed when data to be acquired extends over a few pages.
In addition, memory consolidated image processing LSIs mounted on portable electronics are often driven by a rechargeable battery. Although the loaded battery may have a large charging capacity so that the LSIs can be used for a long time, this prevents the whole electronics from being miniaturized since the weight increases. Therefore, although the capacity of the loaded battery is determined in view of the weight and size to some extent, it has been requested that the power consumption of the LSI should be saved as small as possible.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a memory consolidated image processing LSI capable of accomplishing an efficient power consumption by reducing a first power consumption for accessing a page by the device that the LSI has a size and shape by which an image processing can be most efficiently carried out with respect to the way to segment one of pages constituting a screen when a DRAM is accessed.
In order to accomplish the aforementioned and other objects, according to a first basic construction of the present invention, a memory consolidated image processing LSI comprises: a memory part including a page region for storing image data for a plurality of lattice-like page ranges which are formed by segmenting an image plane corresponding to a display screen and each of which has sides a power of 2 long, and word regions, each of which stores image data for a plurality of word ranges formed by segmenting each of the page ranges and which are assembled to constitute the page region; and an image access part for word-accessing the word ranges after accessing the page ranges by a pre-charge in order to access the memory part. The page region or word region stored in said memory part is set so as to have a multiplied value of a power consumption per one of pre-charges in a power consumption model of a memory by an average number of the pre-charges to be a substantially minimum value, or a multiplied value of a power consumption per one of word accesses in a power consumption model of a memory by an average number of the word accesses to be a substantially minimum value. The substantially minimum value does not mean that the multiplied value completely coincides with the absolutely minimum value, and means that the multiplied value includes proximity values of the minimum value.
According a first aspect of the present invention, in the memory consolidated image processing LSI according to the first basic construction, the page ranges on the image plane wherein image data is stored in the page region of the memory part has a size so that the multiplied value of power consumption per one of the pre-charges in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value.
According to a second aspect of the present invention, in the memory consolidated image processing LSI according to the first basic construction, the word ranges on the image plane wherein image data is stored in the word region of the memory part has a size so that the multiplied value of a power consumption per one of the word accesses in a power consumption model of a memory by an average number of word accesses is the substantially minimum value.
According to a third aspect of the present invention, in t
Kabushiki Kaisha Toshiba
Monestime Mackly
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