Memory configuration scheme enabling parallel decoding of...

Details Memory configuration scheme enabling parallel decoding of... Memory configuration scheme enabling parallel decoding of...

2006-02-07

2006-02-07

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06996767

ABSTRACT:
A memory configuration scheme that enables parallel decoding of a single block of turbo-encoded data is described. In this scheme a single code block is divided into multiple subblocks and decoding is performed on subblocks in parallel. The turbo decoder memory is configured so that subblock decoders can access the common memory resources independently of each other. This scheme is different from existing parallel decoding schemes in that it achieves the parallel implementation by applying multiple decoders to a single code block, not by assigning multiple decoders to multiple code blocks. The advantages of this scheme include minimum memory requirement and minimum decoding latency. The minimum memory requirement results from the fact that it needs memory resources only for a single code block regardless of the number of decoders used. The decoding latency is minimum since decoding of a code block is over when decoding on subblocks is completed.

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