Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-10-17
2002-10-15
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070, C365S230030
Reexamination Certificate
active
06466493
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a memory configuration having memory blocks with redundant memory locations that can be selected via addresses. The invention also relates to a method for accessing redundant memory locations that are provided in columns and rows in a memory configuration having memory blocks.
Information, which is stored in a memory, is deposited in individual memory locations which are provided in a location field having columns and rows. Each memory location can be selected for reading or writing via column and row address lines with the aid of an address that is assigned to the location. To this end, the address lines are connected to column and row decoders. These decode the supplied address and activate column and row address lines corresponding to the address.
As a consequence of the high integration density and the ever smaller grid dimensions, there is an increased susceptibility to defects in the location field, such as defective memory locations or damaged address lines. In order to guarantee a certain minimum capacity of the memory given a definite number of defects, devices are usually provided for replacing the defects. Usually these devices are additional memory locations that can be used in place of the defective locations with the aid of programmable coding elements.
In memories of higher capacity, the memory locations are split into several blocks. Because of the matrix-type configuration of the memory locations, the additional locations must likewise be provided in rows and columns. Using a programmable element, additional lines appertaining to the additional locations are selected in dependence upon the applied address. These elements are programmed via what are known as fuse banks, which contain laser-separable connections. In a test of the memory the addresses that are assigned to defective memory locations are discovered. The fuse banks are then coded such that the additional (redundant) memory locations are accessed it these addresses.
Published European Patent Application EP 0 612 074 A1, which corresponds to U.S. Pat. No. 5,457,655, teaches a column redundancy circuit configuration having a plurality of memory blocks. The programmable coding elements are not strictly allocated to the blocks. Rather, each of the coding elements contains an address coding device and thus can be allocated to an arbitrary memory block.
Experiments have shown that defects often occur clustered in one block. On the other hand, other blocks remain free of errors. The typical errors are individual defects that occur along a column address and/or a row address, or a cluster of adjoining individual defects. The location of these clusters can be determined by testing only after the production of the memory.
In order to be able also to eliminate adjoining individual defects such as this by redundant lines, a high number of redundant lines is needed in every block. But this leads to an increase in the surface area of the chip.
International Publication No. WO 93/21578 therefore proposes a memory configuration and a method for accessing redundant memory locations, wherein the originally supplied address is compared to a preprogrammed address by a redundance block decoder, and, if a match is found, a corresponding redundance word line decoder and redundance bit line decoder of the corresponding memory block is actuated to access a redundant memory location that is addressed by the redundance word line decoder and redundance bit line decoder. The redundant memory location can be provided in a different memory block than that of the original location that must be replaced.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory configuration with a redundancy mechanism which overcomes the disadvantages of the heretofore-known memory configurations of this general type and in which the number of defects that can be eliminated with redundant lines is increased without increasing the number of redundant lines per memory block. It is also an object of the invention to provide a method of accessing redundant memory locations.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
memory blocks having memory locations and redundant memory locations;
the memory locations and the redundant memory locations being organized in rows and columns and being selectable via respective select addresses;
a programmable row decoder and a programmable column decoder respectively allocated to each of the memory blocks for selecting one of the redundant memory locations in a respective one of the memory blocks;
at lease one of the programmable column decoder and the programmable row decoder of at least a given one of the memory blocks being programmed such that the given one of the memory blocks can be selected with a select address corresponding to another one of the memory blocks for accessing given ones of the redundant memory locations assigned to the another one of the memory blocks;
the programmable column decoder and the programmable row decoder allocated to the given one of the memory blocks each including a comparing device for comparing a given portion of the select address to a corresponding preprogrammed address; and
the programmable column decoder and the programmable row decoder allocated to the given one of memory blocks being configured such that the programmable column decoder performs a comparison of the select address to the corresponding preprogrammed address only when the programmable row decoder has not detected a match between the select address and the corresponding preprogrammed address.
The invention has the advantage that a defect in a memory block can be remedied by using the redundant locations of an adjacent memory block. It is thus possible to eliminate more defects in a memory block than there are redundancy lines present in this block.
It is also advantageous that both, redundant column lines and redundant row lines can be used for redundancy.
In accordance with another feature of the invention, the comparing device of the programmable column decoder and the comparing device of the programmable row decoder allocated to the given one of the memory blocks are configured to deny access to the memory locations for the memory blocks except for the given one of the memory blocks, if the comparison of the select address to the corresponding preprogrammed address produces a match.
In accordance with yet another feature of the invention, the select a dress has a first portion for selecting one of the memory blocks, a second portion for selecting one of the columns, and a third portion for selecting one of the rows; the comparing device of the programmable column decoder allocated to the given one of the memory blocks compares the first portion and the second portion of the select address to the corresponding preprogrammed address; and the comparing device of the programmable row decoder allocated to the given one of the memory blocks compares the first portion and the third portion of the select address to the corresponding preprogrammed address.
With the objects of the invention in view there is also provided, a method of accessing redundant memory locations, which includes the steps of:
providing memory locations organized in columns and rows in a memory configuration having memory blocks;
allocating programmable column decoders and programmable row decoders to the memory blocks;
replacing a given one of the memory locations of a given one of the memory blocks by a redundant memory location of another one of the memory blocks by performing a comparison of a select address of the given one of the memory locations to a respectively preprogrammed address of each of the programmable column decoders and to a respective preprogrammed address of each of the programmable row decoders; and
performing the comparison to the respective preprogrammed address of the column decoders only when the comparison to the respective p
Menke Manfred
Plan Manfred
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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