Memory component with configurable multiple transfer formats

Details Memory component with configurable multiple transfer formats Memory component with configurable multiple transfer formats

2001-12-20

2004-06-08

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S217000, C711S219000

Reexamination Certificate

active

06748509

ABSTRACT:

The invention relates to a multiprocessor system of the type comprising a central memory, treatment processors and cache memories associated with treatment processors. It also relates to a process for the exchange of information between central memory and treatment processors via the cache memory associated with each of these processors. It also provides a new integrated circuit component, capable of equipping the multiprocessor system.
It is known that, in the most common known multiprocessor systems, all the information (data, address) is relayed by a common parallel communication bus between the central memory and the various treatment processors, which constitutes a bottleneck: its transfer rate is in effect insufficient to feed all the processors for full efficiency, from a common central memory.
For increasing the information transfer rate, a first solution consists in associating with each treatment processor a cache memory which, by the location of the information, permits reducing the demands on the central memory. However, in the case in which the volume of data shared between processors is substantial, the maintenance of coherence of the data between memories generates complementary information traffic on the communication bus which resists a significant reduction of the overall flow on this bus, and therefor removes a large part of the interest in this solution.
Another solution consists in providing the communication bus in the form of a grid network designed as a “crossbar”, which permits a direct communication between each treatment processor and each subassembly of the central memory (memory bank). However, this solution is very heavy and very costly to achieve because of the very great number of interconnections, and it becomes completely unrealistic beyond about ten treatment processors. Moreover, in the case of multiple demands of several processors on the same memory bank, such a solution implies access conflicts, a source of slowing up the exchanges.
Another more current solution by reason it its architectural simplicity consists in associating a local memory with each treatment processor for storing specific data therein, and storing the transferred data in the common central memory. However, the great deficiency of this architecture is its non-transparency, that is, the need for the programmer to organize the detail of the allocation of data in the various memories, such that this solution is of a very constrained usefulness. Moreover, in the case of high volume of transferred data, it may lead as before to a saturation of the access bus in the central memory.
A solution which has been called “aquarius architecture” has been proposed by the University of Berkeley and consists in improving the aforementioned crossbar solution by combining with the crossbar network, for the shared data, cache memories which are connected to the crossbar network, and for the shared data, distinct cache memories which are connected to a common synchronization bus. This solution contributes a gain in speed of exchange but remains very heavy and very costly to achieve.
The present invention seeks to provide a new solution, permitting considerably increasing the flow rate of information exchange, while retaining an architecture which is transparent for the user, much simpler than the crossbar architecture.
An object of the invention is thus to permit notably increasing the number of treatment processors of the system, while benefitting from a high efficiency for each processor.
Another object is to provide a structure of an integrated circuit component, permitting a very simple realization of the architecture of this new multiprocessor system.
To this end, the multiprocessor system provided by the invention is of the type comprising a central memory (RAM) organized in blocks of information (bi), treatment processors (CPU
1
. . . CPU
j
. . . CPU
n
), a cache memory (MC
j
) connected to each treatment processor (CPU
j
. . . CPU
j
. . . CPU
n
) a cache memory (MC
j
) connected to each treatment processor (CPU
j
) and organized in blocks of information (b
i
) of the same size as those of the central memory, a directory (RG
j
) and its management processor (PG
j
) associated with each cache memory (MC
j
), means for communication of addresses of blocks between processors (CPU
j
) and a central memory (RAM). According to the present invention, the multiprocessor system is provided with:
an assembly of shift registers, termed memory shift registers (RDM
1
. . . RDM
j
. . . RDM
n
), each register (RDM
j
) of this assembly being connected to the central memory (RAM) in such a manner as to permit, in one cycle of this memory, a parallel transfer in read or write of a block of information (b
i
) between said register and said central memory;
shift registers, termed processor shift registers (RDP
1
. . . RDP
j
. . . RDP
n
), each processor shift register (RDP
j
) being connected to the cache memory (MC
j
) of a processor (CPU
j
) in such a manner as to permit a parallel transfer in reading or writing of a block of information (b
i
) between said shift register (RDP
j
) and said cache memory (MC
j
);
an assembly of series links (LS
1
. . . LS
j
. . . LS
n
), each connecting a memory shift register (RDM
j
) and a processor shift register (RDP
j
) and adapted to permit the transfer of blocks of information (b
i
) between the two registers considered (RDM
j
, RDP
j
).
Thus, in the multiprocessor system according to the invention, the exchanges between the cache memories and the associated processors are carried out as in the conventional systems provided with cache memories. By contrast, the exchanges between the central memory and the cache memories is carried out in an entirely original manner.
Each transfer of an information block (b
i
) from the central memory (RAM) to the cache memory (MC
j
) of a given processor (CPU
j
) consists of:
transferring, in a cycle of the central memory, the block (b
i
) of said central memory (RAM) to the memory shift register (RDM
j
) (of the size of one block) which is directly connected to the central memory and which corresponds to the processor (CPU
j
) considered,
transferring on the corresponding series link (LS
j
) the contents of this memory shift register (RDM
j
) to the processor shift register (RDP
j
) (of the same capacity) which is associated with the cache memory (MC
j
) of the processor considered (CPU
j
),
transferring the contents of said processor shift register (RDP
j
) to the cashe memory (MC
j
).
In the opposite direction, each transfer of information blocks (b
i
) from the cache memory (MC
j
) of a given processor (CPU
j
) to the central memory (RAM) consists of:
transferring the block (b
i
) of said cache memory considered (MC
j
) to the processor shift register (RDP
j
) which is associated with said cache memory (MC
j
),
transferring on the corresponding series link (LS
j
) the contents of the processor shift register (RDP
j
) to the memory shift register (RDM
j
), allocated to the processor considered (among the assembly of shift registers (RDM
1
. . . RDM
j
. . . RDMn) connected to the central memory (RAM),
transferring in a cycle of the central memory, the contents of the memory shift register (RDM
j
) to said central memory (RAM).
In these conditions, the transfer of each block of information (b
i
) is carried out, no longer through a parallel bus as is the case in the known systems, but by the series links of high flow rate. These series links permit obtaining comparable times of transfer for each block (b
i
) and even lower than the transfer times in known parallel bus systems. The comparative example given hereinbelow with the current values of the parameter for current technology, illustrates clearly this fact which seems paradoxical.
It is assumed that each block of information (b
i
) is of a size equal to 64 octets.
In the system of the invention, the transfer time between the central memory and a cache memory breaks down into:
a central memory transfer time (RAM)/memory shift register (RDM
j
): 100 nanoseconds (

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