Memory compiler redundancy

Static information storage and retrieval – Read/write circuit – Including signal comparison

Reexamination Certificate

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Details

C365S200000, C365S201000, C365S225700

Reexamination Certificate

active

07460413

ABSTRACT:
An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit. Means are provided in the memory instances for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register.

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