Memory column redundancy scheme

Details Memory column redundancy scheme Memory column redundancy scheme

2007-09-12

2010-11-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

07826285

ABSTRACT:
A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.

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