Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-04-11
2001-05-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189020, C365S205000, C365S230030
Reexamination Certificate
active
06240029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to column-redundancy techniques for integrated-circuit memory devices.
2. Prior Art
Whenever one or more memory cells in a particular column of an integrated-circuit memory chip are defective, the entire memory column is considered to be defective and a redundant memory column is substituted for the defective column. To program a memory chip to substitute a redundant column for a defective memory column, a number of programming fuses are blown with a laser beam. Conventional column-redundancy methodology in an integrated-circuit memory device normally requires a large number of fuses for each redundant column, which uses a considerable area of the integrated-circuit chip.
When a particular Y select address for a redundant column is received in a memory chip with a conventional column-redundancy approach, the memory chip is programmed to enable a redundant senseamp and also to disable a normal senseamp. This is accomplished by blowing one fuse to turn on transfer gates that allow all of the Y-select signals to go to a redundant Y select NAND circuit. Then, since all of the signals are going to the NAND circuit, eight more fuses are blown to stop unwanted Y select signals from getting to the NAND circuit. One more fuse is then blown to disable the normal Y-select NAND circuit enable signal. Blowing ten of nineteen fuses causes the normal senseamp to go to an inactive state and the redundant senseamp to go to an active state.
To connect the redundant senseamp to a particular output buffer, the output terminal of the redundant senseamp is connected through series fuses to each one of eight internal data bus lines, where each internal data buss line connects to a particular output buffer. To connect the redundant senseamp to a particular output buffer seven of eight fuses are required to be blown.
For writing data into the memory chip, eight series fuses are used to connect the internal data bus lines to a common node that goes to the drivers of the redundant bit line and bit inverse columns. To remove the unwanted connections of this scheme, seven additional fuses have to be blown.
For the conventional column redundancy methodology described above, the number of fuses per redundant column is 35 and the number of fuses blown per redundant column is 24. An example of a conventional column redundancy methodology, which illustrates the total number of fuses required for conventional column-redundancy, is a 4 Mbit SRAM with 32 redundant columns. Each of the redundant columns requires 35 for a total of 1120 fuses. For the 4 Mbit SRAM, a minimum of 24 fuses are required to be blown for each redundant column. Therefore, utilizing all 32 of the redundant columns requires a minimum of 768 fuses to be blown. The locations of all of these 1120 fuses must be programmed into the software that controls a laser that is used to blow these fuses. In the fabrication and testing of memory chips that have conventional redundant memory columns, additional time and expense are required to blow all of the fuses for substitution of a redundant memory column for a damaged or otherwise unusable memory column.
Consequently, a need exists for a column-redundancy methodology for an integrated-circuit memory chip that greatly reduces the number of fuses required to be blown for substitution of a redundant column for a defective column.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved column-redundancy technique for a memory chip that greatly reduces the number of fuses that are blown for substituting a redundant memory column for a defective memory column.
In accordance with this and other objects of the invention, a method and apparatus are provided which compares and matches an incoming memory address signal with static signals provided by a fuse array. The static signals represent an address of a defective memory column that is being replaced by a redundant memory in a memory chip. For an exemplary static random access memory SRAM chip according to the invention, each of the redundant columns is provided with an individual senseamp.
The present invention provides column redundancy for a memory, chip which has a plurality of sections, each of which sections is addressed with a section-select address signal. Each section includes a corresponding redundant column for replacement of a damaged, defective, or otherwise unusable memory column in that particular section of the memory.
Each redundant column of the memory is individually connected to a separate redundant-column senseamp that is activated by a memory section-select signal in combination with a BIGHIT signal. The BIGHIT signal indicates that the memory chip has received any address of a defective memory column. All of the output terminals of the redundant column senseamps are connected in common to a redundant internal data bus RDINTDB.
A defective-column-address detector circuit is provided for each memory section. The detector circuit compares each incoming multi-bit memory address signal (for a memory section and a column in that memory section) to an address of a defective memory column and provides an address-hit signal ADDHIT if a match occurs therebetween. A BIGHIT circuit combines the ADDHIT signals for all of the memory sections to provide the BIGHIT signal when any one ADDHIT signal is present.
A 2:1 multiplexer is provided for each output terminal of the memory chip. One input terminal of each of the 2:1 multiplexers is connected to the redundant internal data bus RDINTB. The other input terminal of each of the 2:1 multiplexers is normally coupled to an internal data bus INTDB that is connected to an output terminal of one of the normal senseamps for the memory chip. Each of the 2:1 multiplexers is normally set to connect the second input terminal to its output terminal. Each of the 2:1 multiplexers is selected by a respective output terminal select signal OUTLINE to connect the redundant internal data bus RDINTDB to an associated one of the output terminals of the memory chip;
An output decoder circuit OUTDEC assigns a particular ADDHIT signal for a particular redundant column to a particular OUTLINE signal, which couples a particular redundant column to a particular output terminal, or pin, of the memory chip.
Each of the normal senseamps is connected to a plurality of input terminals coupled to normal memory columns.
The defective column address detector circuit includes an exclusive logic circuit that compares each bit of the multi-bit memory address signal to respective static bits representing an address of a defective column. The static bits for the address of the replaced column are provided by an array of fuses, which are adapted to be blown by a laser beam.
The BIGHIT circuit includes a logic OR circuit for combining the ADDHIT signals. The output decoder circuit OUTDEC includes a circuit that connects an ADDHIT signal to a particular OUTLINE signal. Predetermined fuses are blown to direct the ADDHIT signal to select a particular output pin of the memory chip.
A method provides column-redundancy to a memory chip, including the steps of: connecting an input terminal of each of a plurality of separate redundant senseamps to a respective redundant memory column; connecting in common an output terminal of each of the separate redundant senseamps to a redundant internal data bus (RDINTB); selectively activating only one at a time of the separate redundant senseamps upon receipt of both a memory-section-select signal and a BIGHIT signal, which receipt indicates that an address of any defective memory column has been received by the memory chip, such that only one of the separate redundant senseamps is activated at any one time; connecting the redundant internal data bus (RDINTB) to a first input terminal of each of a plurality of 2:1 multiplexers; connecting a second input terminal of each of the plurality of the 2:1 multiplexers to a respective internal data bus (INTDB) that is connected to an output terminal of a norma
Ho Hoai V.
King Patrick T.
NanoAmp Solutions, Inc.
Nelms David
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