Memory column interface with fault tolerance

Details Memory column interface with fault tolerance Memory column interface with fault tolerance

1990-03-26

1992-04-07

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 102, 36518902, G11C 800

Patent

active

051034247

ABSTRACT:
A memory circuit for controlling writing and reading operations in a large semiconductor memory having multiple modules, some of which are subject to production or environmentally caused defects. Memory modules are arranged in columns and there is a column interface for each column, each module being connected to its column interface by a single-bit data line. Each column interface includes a configuration register that is used to record an association between the memory modules in the column and selected data bit positions of an external data word. The same association is used both during writing operations, wherein data words are written from the data bus to the memory modules, and during reading operations, wherein data words are read from the memory modules to the data bus. The interface may be controlled to write data to and read data from the configuration register itself, and the register is subject to automatic testing for invalid patterns of bits associating the memory modules with data bus bit positions.

REFERENCES:
patent: 4471472 (1984-09-01), Young
patent: 4653050 (1987-03-01), Vaillancourt

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