Memory coherency in a processor-to-bus cycle in a...

Details Memory coherency in a processor-to-bus cycle in a... Memory coherency in a processor-to-bus cycle in a...

1996-06-13

2001-03-20

Sheikh, Ayaz R. (Department: 2781)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S264000, C710S265000, C710S266000, C710S268000, C711S120000, C711S122000, C711S146000, C711S152000, C711S167000, C711S141000, C711S125000, C711S131000

Reexamination Certificate

active

06205507

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to memory coherency in a processor-to-bus cycles in a multi-processor system.
Many computer systems include multiple processors, such as central processing units (CPUs), which may perform various operations requiring access to a main memory. Examples include reading or writing data from or to the main memory. In these systems, several CPUs may perform operations with respect to data stored in a particular main memory address during the same time interval. Furthermore, a particular CPU may retrieve data from the main memory, modify the retrieved data, and then write the modified data to the specified main memory address.
To enhance the speed capabilities of the system, many computer systems have cache memories associated with the CPUs in addition to the system's main memory. The cache memories are used for the temporary storage of data which the CPUs use during performance of various other operations.
Data is typically transferred between the main memory and the CPUs through one or more buses. A central processor controls access to the bus and determines which CPU or other system component will be given access to the bus at any given time. The central processor thus allows specified bus or memory cycles to be performed before performance of other cycles involving the storage, retrieval and transmission of data from one system component to another system component. One purpose of such priority techniques is to ensure that data stored in the main memory does not become stale. These priority techniques thus help prevent one system component from accessing data in the main memory which was previously modified by another system component but which has not yet returned to the main memory.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention features performing a processor-to-bus cycle in a multi-processor computer system. The processor-to-bus cycle is interrupted before completion, and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.
Certain implementations of the invention include one or more of the following features. The operation to save data in memory may include flushing a data queue to the memory. It may also include performing a snoop routine with respect to data in the queue to help ensure that the data stored in the main memory is not stale. A write back operation may be performed as a result of the snoop routine. The processor-to-bus cycle may be a cycle to a peripheral component interface (PCI) bus, and performing an operation to save data may include flushing a PCI-to-memory queue. The processor-to-bus cycle may be interrupted prior to assertion of an address strobe signal. Access to a host bus to perform the snoop routine may be requested in response to detecting the processor-to-bus cycle, and the processor-to-bus cycle may be interrupted in response to the request. Interrupting the processor-to-bus cycle may include denying access to the host bus to the processor that initiated the cycle. Resuming the interrupted cycle may include returning control of the host bus to a distributed controller associated with the processor that initiated the processor-to-bus cycle. Resuming the interrupted cycle may also include granting access to the host bus to the processor that initiated the cycle.
Certain implementations of the invention provide one or more of the following advantages. A processor-to-bus cycle may be interrupted, rather than terminated, and resumed at a later time. As a result, certain bus arbitration periods, during which a determination is made as to which system component will be granted access to a bus, may be eliminated. A savings in time may thus be achieved with respect to performance of some processor-to-bus cycles. In addition, other signals used in connection with processor-to-bus cycles in known techniques may be eliminated.
Other features and advantages of the invention will be more clearly understood upon reading the following description and accompanying drawings and the claims.


REFERENCES:
patent: 5072369 (1991-12-01), Theus et al.
patent: 5163143 (1992-11-01), Culley et al.
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5327570 (1994-07-01), Foster et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5459842 (1995-10-01), Begun et al.
patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5553265 (1996-09-01), Abato et al.
patent: 5590341 (1996-12-01), Matter
patent: 5617557 (1997-04-01), Stevens
patent: 5623625 (1997-04-01), Thompson et al.
patent: 5627993 (1997-05-01), Abato et al.
patent: 5652894 (1997-07-01), Hu et al.
Compaq Computer ProLiant 2000, “QuickSpecs”, Product Buletin, Doc. No. 041C/0595 (May 1995).
Compaq Computer ProLiant 4000, “QuickSpecs”, Product Buletin, Doc. No. 043C/0595 (May 1995).
Compaq Computer Corporatiion “Proliant” 2000 Series Models.
Compaq Computer Corporation “Proliant”4000 Series Models.

Affiliated with

Also associated with

Rating

Memory coherency in a processor-to-bus cycle in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory coherency in a processor-to-bus cycle in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory coherency in a processor-to-bus cycle in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2524601