Memory circuits, systems, and methods with cells using back bias

Details Memory circuits, systems, and methods with cells using back bias Memory circuits, systems, and methods with cells using back bias

1998-09-28

2000-05-09

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365226, 36518909, G11C 1100

Patent

active

060612673

ABSTRACT:
A memory configuration (20). The memory configuration comprises a plurality of memory cells (SCI1, SCI2, SCI3) arranged in a plurality of rows and columns. The memory configuration also comprises a plurality of wordlines (WL.sub.0 -WL.sub.N). Each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period. In addition, each of the plurality of memory cells comprises at least one transistor (e.g., AT3) coupled to receive a back bias. The memory configuration also comprises circuitry for providing a first back bias operable to cause only the at least one transistor in each of the memory cells in the selected row (e.g., WL.sub.0) to have a first threshold voltage, and circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage. The first threshold voltage is different than the second threshold voltage.

REFERENCES:
patent: 5600588 (1997-02-01), Kawashima
patent: 5706226 (1998-01-01), Chan et al.
patent: 5708599 (1998-01-01), Sato et al.

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