Memory circuits preventing false programming

Details Memory circuits preventing false programming Memory circuits preventing false programming

2007-10-09

2009-06-23

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S195000, C365S226000

Reexamination Certificate

active

07551497

ABSTRACT:
Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus, comprising a control terminal, and a level shifter, shifting a voltage level of an enabling signal to a first power voltage from a second power voltage lower than the external programming voltage. When the second power voltage is not ready during power up, the level shifter sets the control terminal of the switching unit to a predetermined logic level such that the switching unit is turned off and the source bus is disconnected from the external programming voltage thereby preventing false programming.

REFERENCES:
patent: 5257239 (1993-10-01), Guo et al.
patent: 5446408 (1995-08-01), Tedrow et al.
patent: 5615162 (1997-03-01), Houston
patent: 5828607 (1998-10-01), Bushey et al.
patent: 6166981 (2000-12-01), Kirihata et al.

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