Memory circuitry for programmable logic integrated circuit...

Details Memory circuitry for programmable logic integrated circuit... Memory circuitry for programmable logic integrated circuit...

2000-11-01

2002-06-04

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040, C365S230030

Reexamination Certificate

active

06400635

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic integrated circuit devices (“PLDs”), and more particularly to memory circuitry for use on PLDs which a user of the PLD can use for various purposes during normal logic operation of the PLD.
Programmable logic devices having relatively large blocks of memory in addition to the usual programmable logic and programmable interconnect are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,550,782, Cliff et al. U.S. Pat. No. 5,689,195, Heile U.S. Pat. No. 6,020,759, Heile U.S. Pat. No. 6,144,573, and Heile U.S. patent application Ser. No. 09/389,995, filed Sep. 2, 1999. The above-mentioned blocks of memory can be connected to the programmable logic and/or input/output (“I/O”) pins of the device via the programmable interconnect. Such blocks of memory can be used for read-only memory (“ROM”), random access memory (“RAM”), content-addressable memory (“CAM”), product-term (p-term) logic, etc. It is known that such blocks of memory can have programmably variable width and depth. For example, a 2 K-bit memory can be configured as 2K one-bit words (“2K×1”), 1K two-bit words (“1K×2”), 512 four-bit words (“512×4”), 256 eight-bit words (“56×8”), 128 16-bit words (“128×16”), etc. It is also known that such blocks of memory can be provided with separate read and write ports so that reading and writing can be done independently at the same time (so-called dual-port operation).
The known programmable logic device memory arrangements of the type described above are sometimes difficult to fully utilize. For example, if a first-in/first-out (“FIFO”) memory having a capacity of eight words of eight bits each (i.e., an 8×8 FIFO) is needed, only 64 bits of a 2K bit memory block are used and the remaining 1984 bits in that block are wasted.
SUMMARY OF THE INVENTION
In accordance with this invention a device is provided having programmable circuitry which includes a plurality of logic components, each having at least one programmable circuit, and a memory coupled to the plurality of logic components and being configurable to include at least two write ports and one read port, the memory being capable of performing multiple write and read operations substantially simultaneously.
In an alternative embodiment the memory of the device is configurable to include at least two read ports and one write port.
In still another alternative embodiment the memory of the device is configurable to include two write ports and two read ports.
In each embodiment each memory cell is accessible via any read port and any write port. This allows the memory to be operated in any of several different modes, including (1) operation as one large memory, or (2) operation as two, effectively separate, memories having any of a wide range of relative sizes.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.


REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5010519 (1991-04-01), Yoshimoto et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5590087 (1996-12-01), Chung et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5715197 (1998-02-01), Nance et al.
patent: 5901079 (1999-05-01), Chiu et al.
patent: 5933023 (1999-08-01), Young
patent: 6011744 (2000-01-01), Sample et al.
patent: 6020759 (2000-02-01), Heile
patent: 6052327 (2000-04-01), Reddy et al.
patent: 6144573 (2000-11-01), Heile
“Implementing Dual-Port RAM in FLEX 10K Devices,” Application Note 65, Altera Corporation, San Jose, CA, Feb. 1996, ver. 1, pp. 1-8.
1999 Xilinx Data Book, Xilinx, Inc., San Jose, CA, 1999.

Affiliated with

Also associated with

Rating

Memory circuitry for programmable logic integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuitry for programmable logic integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuitry for programmable logic integrated circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2971019