Memory circuit with stress circuitry for detecting defects

Details Memory circuit with stress circuitry for detecting defects Memory circuit with stress circuitry for detecting defects

1994-07-19

1996-10-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365203, G11C 1300

Patent

active

055703178

ABSTRACT:
A memory circuit is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit comprises a memory cell array coupled to bit lines, an access circuit coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.

REFERENCES:
patent: 4991137 (1991-02-01), Matsumoto
patent: 5029137 (1991-07-01), Hoshi
patent: 5062079 (1991-10-01), Tsuchida et al.
patent: 5138579 (1992-08-01), Tatsumi et al.
patent: 5157631 (1992-10-01), Shimogawa
patent: 5446694 (1995-08-01), Tanaka et al.

Affiliated with

Also associated with

Rating

Memory circuit with stress circuitry for detecting defects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit with stress circuitry for detecting defects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit with stress circuitry for detecting defects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1790511