Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-10-22
2004-08-10
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189040, C365S189011
Reexamination Certificate
active
06775191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to random access memory circuits and, more particularly, to address path configurations within memory circuits.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Random access memory (RAM) is generally used to refer to memory to which data can be written and from which data can be read. More specifically RAM may refer to memory with which data can be written to and read from randomly rather than in a set sequence. In many cases, the locations at which data is written and stored may be accessed by address paths of the RAM circuit. In particular, the addresses at which data may be written to or read from may be specified by inputs to the address paths. In this manner, an operation of a RAM memory circuit may include addressing particular memory locations and either writing to or reading from the locations. In order to insure that valid data is written to or read from a correct memory location, the write and/or read cycles of a RAM memory circuit may include specifications which stipulate the duration of address, write, and/or read operations of the circuit.
For example, “access time,” as used herein, may refer to the period from which an address is asserted for a read operation to a time at which data at such an address is considered valid at the chip outputs. “Valid,” as used herein, may refer to a state in which a specified parameter, such as data, is considered to be correct. In addition, the “assertion” of an address may refer to the input of the address along the address path of the circuit. Consequently, a valid bit may not be read from a memory location until after the memory location is identified and the data at such a memory location is considered valid. A duration specified for the write operation of a memory circuit may, on the other hand, include “address hold time.” “Address hold time,” as used herein, may refer to the time for which an address of one or more memory cells is held after a write operation is terminated. Such a time range may be used to insure that data from a write operation is not inadvertently written to a memory location subsequently addressed by the operation of the circuit.
In general, it is desirable to minimize the access time and/or the address hold time, such that the overall operating speed of the memory circuit may be increased. One manner with which to minimize address hold time is to incorporate an intentional delay within the address paths of the memory circuit. Such a configuration may allow the address of a memory location to be de-asserted a relatively short time after, or in some embodiments, immediately subsequent to the end of a write operation. More specifically, the incorporation of an intentional delay within address paths of a memory circuit may increase the time for which an address of a memory location is identified, thereby preventing a previous write operation from inadvertently writing to a subsequent address location. Consequently, the time used to hold an address subsequent to a write operation of a circuit may be reduced or eliminated. However, the incorporation of an intentional delay within the address paths of a circuit increases the time for which addresses of memory locations are identified for the read operations as well as for the write operations of the circuit. As a result, the amount of time needed to access valid data during a read operation of the circuit is increased relative to circuits which do not include an intentional delay within the address paths of the circuit. In other words, the incorporation of an intentional delay within the address paths of a circuit may increase the access time of the read operations of the circuit. Consequently, the configuration of including an intentional delay within the address paths of a circuit may reduce the operating speed of the read operations of the memory circuit.
Therefore, it may be advantageous to develop a memory circuit which reduces address hold time without increasing the access time of the read operations of the device. In particular, it may be beneficial to fabricate a memory circuit which reduces address hold time for the write operations of the memory circuit while maintaining the time at which a valid bit may be read from the memory cell.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a memory circuit that is adapted to identify one or more memory cells within a first time interval for a write operation of the circuit and identify the one or more memory cells within a second time interval for a read operation of the circuit. Preferably, the first time interval is different than the second time interval. More specifically, the first time interval is preferably greater than the second time interval. In yet other embodiments, however, the first time interval may be less than the second time interval. In any case, the memory circuit described herein may include an address path which includes a different circuit path for the read operations than for the write operations of the circuit. More specifically, the memory circuit described herein may include an address path having a first circuit path for the write operation and a second circuit path for the read operation, wherein the first and second circuit paths are different. “Address path,” as used herein, may refer to a portion of the memory circuit which is adapted to identify memory cells for read and write operations of the circuit. As such, the address path of the memory circuit described herein may be one of a plurality of address paths within the memory circuit having similar components and circuit path configurations.
In general, the first circuit path of the address path described herein includes a means for intentionally delaying the identification of the memory cells for the write operation of the circuit. In some cases, the means for intentionally delaying the identification of the memory cells for the write operation may include a delay circuit, such as a resistor, capacitor, logic inverter, and/or any means used in circuit fabrication to intentionally delay the transmission of a signal along a logic path or circuit path. In some cases, the second circuit path may be absent of such a means for intentionally delaying the identification of memory cells for the read operation of the circuit. Alternatively, the second circuit path may include a means for intentionally delaying the identification of memory cells for the read operation of the circuit.
In any case, the means for intentionally delaying the identification of memory cells for the write operation of the memory circuit described herein may be arranged along a variety of locations of the address path. For example, in some cases, the address path may include at least two decoded address lines coupled to a main address line by a logic decoder. In some embodiments, the means for intentionally delaying the identification of memory cells for the write operation of the memory circuit may be arranged along the main address line. In other embodiments, the means for intentionally delaying the identification of memory cells for the write operation of the memory circuit may be alternatively arranged along one of the decoded address lines. In yet other cases, the means for intentionally delaying the identification of memory cells for the write operation of the memory circuit may be arranged within the logic decoder. In any case, the memory circuit described herein may further include additional means for intentionally delaying the identification of memory cells for the write operation of the memory circuit in some embodiments. Such an additional means may be arranged along another of the decoded address lines of the address path, the main address line, and/or within the logic decoder.
In some cases, the circuit path adapted for identifying the memory cells during the write operations of the circuit may be included in a shunt extending from the circuit path adapted for ide
Gibbs Gary A.
Pancholy Ashish
Yuh Jong Hak
Conley & Rose, P.C.
Daffer Kevin L.
Le Thong Q.
Lettang Mollie B.
Silicon Magnetic Systems
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