Memory circuit with noise preventing means for word lines

Details Memory circuit with noise preventing means for word lines Memory circuit with noise preventing means for word lines

1983-09-12

1986-07-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Noise suppression

365203, G11C 702

Patent

active

046023550

ABSTRACT:
A memory circuit provided with improved noise preventing circuits allowing a high-density arrangement of memory cells is disclosed. The memory circuit comprises a cross-coupled circuit provided for adjacent two word lines. The cross-coupled circuit suppress the potential of one of the adjacent two word lines to a reference level when the other of the adjacent two word lines takes a selection level or a level near the selection level.

REFERENCES:
patent: 4133049 (1979-01-01), Shirato
patent: 4280198 (1981-07-01), Heuber et al.

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