Memory circuit with increased operating speed

Details Memory circuit with increased operating speed Memory circuit with increased operating speed

1979-10-31

1981-11-10

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

G11C 700

Patent

active

043002137

ABSTRACT:
Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.

REFERENCES:
patent: 4099265 (1978-07-01), Abe
patent: 4162540 (1979-07-01), Ando
patent: 4168537 (1979-09-01), Uchida

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