Memory circuit with improved word line noise preventing circuits

Details Memory circuit with improved word line noise preventing circuits Memory circuit with improved word line noise preventing circuits

1986-07-01

1988-08-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Noise suppression

365189, G11C 1140, G11C 1300

Patent

active

047649020

ABSTRACT:
A memory circuit provided with an improved word line noise preventing circuit is disclosed.
The memory circuit is one of the type having a pair of digit lines, a plurality of word lines intersecting with the digit lines, a plurality of memory cells, a sense amplifier coupled to the pair of digit lines and a plurality of noise preventing circuits provided for the word lines. The memory is featured in that the noise preventing circuits are disenabled during the period when the sense amplifier amplifies the voltage difference between the pair of digit lines.

REFERENCES:
patent: 4280198 (1981-07-01), Heuber et al.
patent: 4409678 (1983-10-01), Takemae et al.
patent: 4602355 (1986-07-01), Watanabe
patent: 4610002 (1986-09-01), Kaneko

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