Memory circuit with extended valid data output time

Details Memory circuit with extended valid data output time Memory circuit with extended valid data output time

1990-08-27

1993-05-11

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Signals

36518905, 307594, 307265, 307597, 307601, 307603, G11C 700

Patent

active

052107159

ABSTRACT:
A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

REFERENCES:
patent: 4764900 (1988-08-01), Bader et al.
patent: 4820942 (1989-04-01), Chan

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