Memory circuit with dynamic redundancy

Details Memory circuit with dynamic redundancy Memory circuit with dynamic redundancy

2005-08-23

2005-08-23

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S189120

Reexamination Certificate

active

06934202

ABSTRACT:
The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

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