Memory circuit with dynamic redundancy

Details Memory circuit with dynamic redundancy Memory circuit with dynamic redundancy

1998-05-29

1999-11-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, 3652257, G11C 700

Patent

active

059826797

ABSTRACT:
The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

REFERENCES:
patent: 4780851 (1988-10-01), Kurakami
patent: 5255217 (1993-10-01), Tan
patent: 5255227 (1993-10-01), Haeffele
patent: 5471427 (1995-11-01), Murakami et al.
patent: 5498990 (1996-03-01), Leung et al.
patent: 5574729 (1996-11-01), Kinoshita et al.
patent: 5592632 (1997-01-01), Leung et al.
patent: 5613077 (1997-03-01), Leung et al.
patent: 5666480 (1997-09-01), Leung et al.

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