Memory circuit with built-in cache memory

Details Memory circuit with built-in cache memory Memory circuit with built-in cache memory

1997-07-17

1999-03-30

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711113, 711118, 711119, 711120, 711202, 36523003, 365203, 365233, G11C 1134

Patent

active

058901868

ABSTRACT:
When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

REFERENCES:
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5317540 (1994-05-01), Furuyama
patent: 5361227 (1994-11-01), Takana et al.
patent: 5504709 (1996-04-01), Yabe et al.
patent: 5517454 (1996-05-01), Sato et al.

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