Memory circuit with active load

Details Memory circuit with active load Memory circuit with active load

1988-06-24

1989-07-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

365208, 365227, 307530, G11C 700, G11C 1140

Patent

active

048456721

ABSTRACT:
A memory circuit incorporates a plurality of memory cells arranged in matrix form, with a data line drive circuit having an active load circuit including two MOS transistors, operating as resistive elements during writing, and connected to the data line and the inverted data line of the cells. A differential amplifier is connected to the data line and inverted data line, and a plurality of constant current sources are connected to the transistors of the differential amplifier, with switching means causing one constant current source to be nonconductive during a write operation, with at least one of the current sources being normally on during reading and writing.

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