Memory circuit test system using separate ROM having test values

Details Memory circuit test system using separate ROM having test values Memory circuit test system using separate ROM having test values

1991-06-10

1994-05-24

Lee, Benny

Static information storage and retrieval

Read/write circuit

Testing

371 211, G11C 700

Patent

active

053155530

ABSTRACT:
A memory test method and system are described which comprises a first memory array and a second memory array coupled to a plurality of row address lines within a memory system. During the testing of the memory system, row decode logic is used to sequentially access each of the row address lines The second memory array stores a predetermined value associated with each of the row address lines. Accordingly, accuracy of the row decode logic and continuity of the row address lines can be verified without the necessity of programming each memory location within the first memory array.

REFERENCES:
patent: 4429388 (1984-01-01), Fukushima et al.
patent: 4862418 (1989-08-01), Cuppens et al.
patent: 5031152 (1991-07-01), Doyle

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