Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-02-15
2003-05-20
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S189020, C365S230020
Reexamination Certificate
active
06567323
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to memory circuit failure correction and more particularly to multiple row and multiple column redundancy correction for memory circuits in a memory bank.
BACKGROUND OF THE INVENTION
Memory banks comprising multiple memory circuits in a configuration having a plurality of columns and a plurality of rows are extensively used for data processing. Although such memory circuits are manufactured to be reasonably reliable, there are occasions when single or multiple bit failures in either columns or rows will corrupt the data to be processed. This is an intolerable condition. Significant effort has been expended to develop techniques for repair of a memory circuit to insure uninterrupted and continuous processing of data. To repair memory circuits the failing bits are detected during post manufacture testing of the memory. An important issue in the correction of memory circuit failure is to minimize the potential for data loss or data corruption. The high speed processing systems of today that are processing gigabytes or terabytes of information require reliable circuit failure correction prior to being placed into operation.
Heretofore, complex systems have been developed for correcting a memory circuit failure. One solution to correct memory circuit failure relied on redundancy control coupled to one or more banks of memory circuits arranged in a configuration having a plurality of columns and a plurality of rows. This solution to memory circuit failure utilized one redundant column stick and/or one redundant row stick coupled to the memory bank. For purposes of this disclosure, a row stick is a group of adjacent rows sharing address decode. Likewise, a column stick is a group of adjacent columns sharing address decode. A redundancy controller responded to identification of a column stick failure to activate a shift multiplexer to activate the redundant column stick to correct for a column stick identified as having a memory circuit failure. A column stick failure is defined as having one or more bad bits within the column. This activation of the redundant column stick to correct for the column containing the memory circuit failure was achieved by shifting each column stick between the redundant column stick and the failed column stick, thereby effectively replacing the failed column stick with the redundant column stick through shift control. Similarly, correction of a failure in a row stick of the memory bank was achieved by shifting the redundant row stick into the memory bank to correct for the row stick of memory circuits containing a failed circuit. Again, this was achieved by shifting each row stick between the redundant row stick and the failed row stick, thereby in effect replacing the failed row stick with the redundant row stick.
As the size of memory banks have increased due to the demand for processing large amounts of data, the single column stick and/or single row stick redundancy correction techniques do not provide the level of repair required for large memory banks. Additional correction is required, either in the row direction of a memory bank or in the column direction or both to insure adequate correction of memory circuit failure.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided flexible column stick redundancy of a multi-column stick memory bank having a plurality of rows of memory circuits. Two redundant column sticks of memory circuits, one on each end of the memory bank, enables any two bad column sticks in the memory bank to be replaced utilizing shift multiplexing. The output lines from each column stick of memory circuits terminate at a bank of shift elements in a shift multiplexer that responds to a shift control signal to perform redundant column stick substitution as required by the shift control signals of a redundancy controller. When the memory bank is post-manufacture tested and found to be functioning without failure, the redundant column sticks are not used and the data lines of the operating column sticks of the memory bank flow straight through the shift multiplexer.
Further in accordance with the present invention, there is provided a memory bank having flexible column stick redundancy. The memory has a multi-column stick configuration, each column stick comprising a plurality of data lines. A plurality of redundant column sticks provide flexible column stick redundancy, where each redundant column stick comprises a plurality of data lines. A redundancy controller identifies a fault in the operation of a column stick in the memory bank and in response generates a shift control signal. A shift multiplexer responds to the shift control signal to activate one of the plurality of redundant column sticks to correct for the identified faulty operating column stick in the memory bank. This correction is achieved by shifting each of the column sticks between the redundant column stick and the failed column stick such that the column stick adjacent the failed column stick takes over the data processing for the failed column stick.
The shift multiplexer in the memory bank having flexible column stick redundancy comprises a plurality of shift elements equal in number to the multi-column stick configuration of the memory. Each shift element of the plurality of shift elements responds to the shift control signal to shift to an adjacent column stick in the memory bank between the redundant column stick and the faulty operating column stick.
In addition, in accordance with the present invention, there is provided a memory bank having flexible row stick redundancy. The memory bank has a multi-row stick configuration with each row stick comprising a plurality of columns. A plurality of redundant row sticks are positioned in association with the row sticks of the memory bank with each redundant row stick comprising a plurality of columns. A redundancy controller identifies in post-manufacture testing a faulty operating row stick and generates a shift control signal. This shift control signal is applied to a shift multiplexer that responds thereto to activate a redundant row stick to correct for an identified faulty operating row stick in the memory bank.
In accordance with the present invention, there is provided a memory bank having flexible row redundancy wherein a shift multiplexer as a part thereof comprises a plurality of shift elements equal in number to the multi-row stick configuration of the memory bank. Each shift element of the plurality responds to the shift control signal to shift to an adjacent row stick in the memory.
A memory bank implemented in accordance with the present invention provides efficient and flexible column and row redundancy upon the post-manufacture testing and detection of faulty operating rows or columns. A further advantage of a memory bank implemented in accordance with the present invention is the lack of a requirement of column or row address comparison to determine if a defective column or row is being addressed.
REFERENCES:
patent: 5555522 (1996-09-01), Anami et al.
patent: 6278678 (2001-08-01), Iida
Pitts Robert L.
Timmons Clayton O.
Brady III W. James
Lam David
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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