Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure
Reexamination Certificate
1999-04-13
2001-03-06
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Mesa structure
C257S401000, C257S618000, C365S189011, C365S230010
Reexamination Certificate
active
06198158
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuits, and more specifically to a semiconductor structure having an increased ratio of usable to unusable substrate surface area. The usable substrate area is where transistors and other active devices are disposed.
BACKGROUND OF THE INVENTION
As customers continue to push for smaller, higher-performance integrated circuits (ICs), IC manufacturers continue their efforts to squeeze more transistors and other components onto smaller dies. For example, the present trend is toward memory circuits that have greater storage capacities but that are no larger than their predecessors.
One technique for increasing an IC's component density is to reduce the minimum feature size of a process—the minimum allowable width of, e.g., a transistor gate or an interconnection line—and thus reduce the sizes of the components themselves. Although manufacturers have made great strides in this area over the last few years, there are problems, such as degradation of transistor performance at smaller sizes, that they must overcome before the minimum feature size can be further reduced.
Another density-increasing technique is to use silicon-trench isolation (STI) instead of local oxidation of a semiconductor (LOCOS). But although STI significantly increases the ratio of usable to unusable substrate area as compared to LOCOS, the widths of the STI regions can be no narrower than the minimum feature size, and thus cannot be reduced until the minimum feature size is reduced.
SUMMARY OF THE INVENTION
In one aspect of the invention, a semiconductor structure includes a first substrate portion having a surface, and a first active region disposed in the first substrate portion. An isolation region is disposed on the first substrate portion outside of the first active region and extends out from the surface. A second substrate portion is disposed on the isolation region, and a second active region is disposed in the second substrate portion.
Thus, by disposing portions of the substrate on the isolation regions, a manufacturer can dramatically increase the usable area of the substrate.
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Dorsey & Whitney LLP
Eckert II George C.
Micro)n Technology, Inc.
Saadat Mahshid
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