Memory circuit having compressed testing function

Details Memory circuit having compressed testing function Memory circuit having compressed testing function

2002-10-15

2004-05-04

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S185190, C365S185090, C365S210130, C365S200000, C365S049130

Reexamination Certificate

active

06731553

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit having a compressed testing function, and more particularly to a memory circuit which, lowering the test compression ratio, can increase the salvage ratio of defective cells and increase the simultaneous measurement factor of test equipment.
2. Description of the Related Art
Recently, the trend in semiconductor memories incorporated in portable information terminals, etc. has been toward increasingly large capacity, due to such factors as the storage of image data. As a result, testing time of these memory circuits with increased capacity has tended to become longer, and demand for memory circuits with shorter test time has appeared.
In testing large capacity memory circuits, simultaneous measurement is performed on a plurality of memory chips, connected in parallel to the test equipment. In order to measure simultaneously even more memory chips, even in the face of the limited number of probes built into the test equipment, the output of the memory chips is compressed and a reduction is made in the number of outputs from each. For example, in memory chips with 16-bit output, during test operation, the 16-bit output is compressed by {fraction (1/16)}
th
and made into a 1-bit output. In this way, it is possible to measure simultaneously a number of memory chips equal to the number of probes of the test equipment and the test time required for each chip can be reduced to {fraction (1/16)}
th
.
However, for large capacity memory circuits, it is necessary to provide redundant memory cells and make a configuration that can salvage defective bits. When the compression ratio during testing is increased, in the case that defective bits are discovered it is necessary to replace with redundant memory a number of memory cells corresponding to the compression ratio. For example, if the test compression ratio is {fraction (1/16)}
th
, in the case that a defective bit is discovered, it is not clear which bit of the 16 bits subject to compression is the defective one and as a result, all of the 16 bits of memory cells must be replaced with redundant cells. Consequently, when compression ratio is increased during testing, it may invite the problem that the rate of salvaging defective cells decreases.
As indicated above, what is required is to shorten testing time while also preventing any reduction in the salvage ratio of defective cells. In other words, what is required is to make the compression ratio during testing as low as possible and further to make the number of memory chips which can be simultaneously measured during testing as large as possible.
SUMMARY OF THE INVENTION
To address this, an object of the present invention is to provide a memory chip which keeps the output bit compression ratio during testing as low as possible and enables the output of compressed data from as few output terminals as possible.
In order to achieve the above-indicated object, one aspect of the present invention is to provide a multi-bit output configuration memory circuit comprising: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals.
Responding to each of a plurality of test commands, the compressed output of the M groups of L-bit output is outputted in time shared. Likewise, responding to the test control signals of the external terminals, which follow a common test command, the compressed output of the M groups of L-bit output is outputted in time shared. In this way, the salvage rate of redundant cells can be increased and the simultaneous measuring factor of the test equipment can be increased.


REFERENCES:
patent: 5652725 (1997-07-01), Suma et al.
patent: 5793685 (1998-08-01), Suma
patent: 6324087 (2001-11-01), Pereira
patent: 04-328399 (2002-11-01), None

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