Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-03-01
2003-09-23
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185090
Reexamination Certificate
active
06625071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit such as a flash memory or the like, and more particularly to a memory circuit which has a block address substituting function, and which salvages defective cells while using the memory cell region without any waste, and allows linear access.
2. Description of the Related Art
In the case of miniaturized semiconductor memory circuits, defective cells are generated as a result of the effects of contamination and the like, so that the yield tends to drop. Various methods have been proposed and realized in order to salvage such defective cells. The most common method is a redundant memory system in which a small-capacity redundant memory cell region is formed in addition to the ordinary memory cell region, and defective cells in the ordinary memory cell region are replaced by cells in the redundant memory cell region.
FIG. 1
is a diagram which illustrates a defective-cell salvage system utilizing conventional redundant memory cells. As is shown in
FIG. 1A
, the memory circuit has an ordinary memory cell region MC and a redundant memory cell region RMC. This is an example in the case of a flash memory, and the ordinary memory cell region MC is constructed from eight memory blocks MB
0
through MB
7
, and the redundant memory cell region RMC has a capacity corresponding to a single memory block. Furthermore, as is shown in
FIG. 1B
, when defective cells are generated in the memory blocks MB
1
, MB
2
, MB
5
and the like, these defective cells are replaced by cells in the redundant memory cell region RMC.
However, in the case of a defective cell salvage system utilizing such a redundant memory cell region, only the capacity of the ordinary memory cell region MC can be used at the most, whether the memory is completely good with no defective cells, or whether the memory is partially defective with some defective cells. Accordingly, the memory cells contained in the chip cannot be used effectively, and this is undesirable. Furthermore, the chip area is increased as a result of the installation of a redundant memory cell region.
Another defective cell salvage system is a method in which the uppermost address of the memory circuit is fixed when a defective block is generated, an access to half of the real memory cell region containing the defective block is prohibited, and this real memory cell region is used as a half-good product. In this system, special processing such as the prohibition of access by comparing addresses supplied from the outside with the address of the defective block or the like is unnecessary.
However, in the case of such method, if even one block is defective, the half of the memory cell region that contains this block becomes unusable, so that even if the half of the memory cell region that has become unusable contains non-defective blocks, these blocks cannot be utilized, and are therefore wasted.
Still another defective cell salvage system is a method in which the memory controller of the system mounting the memory circuit is informed of the addresses of memory blocks containing defective cells, and when an access to a defective block occurs, the access to this block is disabled on the memory controller side, so that access to defective blocks is avoided, in a manner similar to the method used in a hard disk or the like.
In the case of such a method, however, an excessive burden is placed on the system side, and the memory circuit cannot be accessed with a sequential increment or decrement of addresses, so that this method is not suited to memory applications in which there is (for example) frequent linear accessing of image data.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a memory circuit equipped with a defective cell salvage function which allows the use of good memory cells formed on the chip with as little waste as possible.
Furthermore, another object of the present invention is to provide a memory circuit which salvages defective cells in the memory circuit without placing a burden on the system side, and which allows sequential access.
In order to achieve the abovementioned objects, one aspect of the present invention is a memory circuit which is capable of salvaging defective cells, and which comprises a plurality of memory blocks each having a plurality of memory cells, a region which stores a block address of defective memory block that has defective cell, and a comparator circuit which compares the block address that is an object of access with the block address of the defective memory block, and detects access to the defective memory block, wherein in case where the comparator circuit detects access to the defective memory block, this defective memory block is replaced by the memory block that has the uppermost address (or lowermost address) among the plurality of memory blocks. In case where a plurality of defective memory blocks are present, the defective memory blocks are replaced with substitutive memory blocks having block addresses in order from the uppermost bit (or lowermost bit).
In the abovementioned construction, in case where a block address accessed from the outside is the address of the defective memory block, the block address of this defective memory block is replaced by the block address of the uppermost (or lowermost) memory block. Alternatively, in cases where a block address accessed from the outside is the address of a defective memory block, the memory block with the uppermost (or lowermost) address is selected instead of the defective memory block. Accordingly, if this system is viewed from the outside, good memory blocks are assigned in order from the lowermost address (or uppermost address), and all good memory blocks can be accessed.
In a preferred embodiment, the substitutive memory blocks that are substituted for the defective memory blocks are assigned in order from the uppermost address (or lowermost address) among a plurality of memory blocks. Accordingly, the memory circuit has a memory region which stores substitutive block address corresponding to the defective block address, and has a switching circuit which replaces the defective block address with substitutive block address when it is detected by the comparator circuit that the block address being the object of access coincides with defective block address.
Alternatively, in another preferred embodiment, substitutive candidate memory block region which is substituted for defective memory block is installed in the uppermost address (or lowermost address) of a plurality of memory blocks, and in case where it is detected by the comparator circuit that block address being the object of access coincides with defective block address, a selection signal for memory block inside the substitutive candidate memory block region is activated. Furthermore, in cases where no defective memory block is present, all of the memory blocks including the substitutive candidate memory block region within the plurality of memory blocks can be accessed.
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patent: 5621690 (1997-04-01), Jungroth et al.
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patent: 5914907 (1999-06-01), Kobayashi et al.
patent: 55-70998 (1980-05-01), None
Ikeda Mitsutaka
Kurita Toshiyuki
Nakai Tsutomu
Yamashita Koji
Arent Fox Kintner Plotkin & Kahn
Nguyen Tan T.
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