Memory circuit having a plurality of cell arrays

Details Memory circuit having a plurality of cell arrays Memory circuit having a plurality of cell arrays

1985-06-20

1988-08-30

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365189, G11C 1140, G11C 1300

Patent

active

047681713

ABSTRACT:
A semiconductor memory circuit which can operate with reduced value of peak currents.
The memory circuit includes two or more memory cell arrays each having a plurality of memory cells and a peripheral circuit for achieving selective access operation is provided for each array. At least a timing signal and its delayed timing signals are generated in response to a control signal. Both of the timing signal and the delayed timing signal are used to enable the peripheral circuits at different timing.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 3969706 (1976-07-01), Proebsting et al.

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