Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-12-12
1999-07-27
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Testing
36518518, 36518905, G11C 700
Patent
active
059301880
ABSTRACT:
An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true V.sub.th measurement test implemented by such circuit. The memory circuit includes circuitry for implementing a true V.sub.th measurement test mode in which an external voltage (or a sequence of external voltages) is applied to an external pad, and a test voltage at least substantially equal to such external voltage (or a sequence of test voltages, each at least substantially equal to one of a sequence of external voltages) is applied directly to the control gates of all or selected ones of rows of the cells (e.g., to all or selected ones of the wordlines of the array). In preferred embodiments, each memory cell is a nonvolatile memory cell such as a flash memory cell. In preferred embodiments, the memory circuit includes circuitry for allowing application (directly to the control gates) of test voltages having a broad range of selected values, including values much greater than and values much less than the memory circuit's internal supply voltage. In accordance with the invention, a memory circuit can operate in true V.sub.th measurement test modes in which a test voltage substantially equal to the external voltage is applied to the control gates of selected ones of the cells, and the cells are read using the same circuitry (e.g., a sense amplifier) that would be used to execute a normal read operation.
REFERENCES:
patent: 5499212 (1996-03-01), Amanai
patent: 5539689 (1996-07-01), Aoki
patent: 5539699 (1996-07-01), Sato et al.
patent: 5677885 (1997-10-01), Roohparvar et al.
patent: 5751944 (1998-05-01), Roohparvar et al.
Micro)n Technology, Inc.
Nguyen Viet Q.
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