Memory circuit comprising redundant memory areas

Details Memory circuit comprising redundant memory areas Memory circuit comprising redundant memory areas

2008-05-13

2008-05-13

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S723000, C365S201000

Reexamination Certificate

active

07373562

ABSTRACT:
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a first setting state, to address the assigned redundant memory area in the event of addressing of the regular memory area with a memory address determined by the first setting state, each redundancy circuit, in a second setting state, addressing the assigned redundant memory area in a manner dependent on an activation signal.

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German Patent Office Examination Report dated Feb. 3, 2005.

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