Memory circuit capable of replacing a faulty column with a spare

Details Memory circuit capable of replacing a faulty column with a spare Memory circuit capable of replacing a faulty column with a spare

1990-10-23

1992-11-10

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Bad bit

36518902, 36523002, 371 102, 371 103, G11C 700, G06F 1120

Patent

active

051630230

ABSTRACT:
A memory circuit comprises a memory array having a plurality of memory cells arranged in rows and columns. Column select circuits enable access to the columns in the array. Each column select circuit is associated with a respective group of the columns and is arranged to access a selected one of the columns in the respective group. At least one spare memory column is provided. Also included are a plurality of read/write circuits associated respectively with the groups, and with the spare memory column, for reading or writing data bits between a data bus and the columns selected by the column selected circuits. Routing circuitry is connected between the read/write circuits and the data bus and is programmable with information identifying at least one faulty column. The routing circuitry is operable in response to an attempted access to the faulty column by disconnecting from the data bus the read/write circuit associated with the group containing the faulty column and connecting to the data bus the read/write circuit associated with the spare column thereby to transfer data between the spare column and the data bus.

REFERENCES:
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patent: 4459685 (1984-07-01), Sud et al.
patent: 4604730 (1986-08-01), Yoshida et al.
patent: 4672581 (1987-06-01), Waller
patent: 4908798 (1990-03-01), Urai
"Circuit implementation of fusible redundant addresses on RAMs for productivity enhancement", Fizgerald and Thomas, IBM J. Res. Develop. vol. 24 No. 3, May 1980.
Bechtle, B. et al., "On Chip redundancy scheme", IBM Technical Disclosure Bulletin, vol. 22, Mar. 1980.
"An Experimental 1M bit CMOS RAM with Configurable Organization and Operation", William et al. IEEE Journal of Solid State Circuits, vol. 23 No. 5, Oct. 1988.

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